In example scenario, a particular time-interleaved digitizing system that includes two or more interleaved digital converters can be used to provide a high sample rate for converting analog signals to digital signals. For example, a time-interleaved analog-to-digital converter (ADC) may include N parallel ADCs where each ADC samples data every Nth cycle of a sample clock. The timing of the ADCs involves complex multiplexing and timing circuitry. Such complex architectures, however, can increase gate count and current consumption, which may not be acceptable for some low-power applications.